IC 74157 PDF
Quad 2-line to 1-line Data Selectors/multiplexers. This X24C02 device has been acquired by IC Microsystems Sdn Bhd from Xicor, Inc. The X24C02 is. The LSTTL / MSI SN54 / 74LS is a high speed Quad 2-Input Multiplexer. Four bits of data from two sources can be selected using the common Select. S, 1 •, 16, Vcc. 1I0, 2, 15, E. 1I1, 3, 14, 4I0. 1Y, 4, 13, 4I1. 2I0, 5, 12, 4Y. 2I1, 6, 11, 3I0. 2Y, 7, 10, 3I1. GND, 8, 9, 3Y. Pin, Symbol, Description. 1, S, common data.
|Published (Last):||26 August 2008|
|PDF File Size:||12.54 Mb|
|ePub File Size:||11.32 Mb|
|Price:||Free* [*Free Regsitration Required]|
The integrated circuit is a comparator 4 bitsi.
To contact the author. For example for a multiplexer with 4 waysone needs 2 entries of order. Form of the perso pages. Figure 29 represents the diagram symbolic system and the mechanical equivalent of a multiplexer with 4 ways.
Its equation is thus A. Electronic forum and Infos. Static page of welcome.
When this entry is with state 1it is the data Bi which is transferred in Yi. A multiplexer can be compared with a mechanical switch.
Nibble Multiplexer: | Education Progresses Best When Knowledge is Shared Openly and Freely
How to make a site? High of page Preceding page Following page. Using one or several entries of order, one switches one of the inputs towards the exit. Thus, one can compare numbers of 8, 12, 16 bits…. In this chapter, we will examine logical circuits very much used to switch data: We will see how to produce using logical doors a comparator of 2 binary digits.
The number of the inputs of a multiplexer defines the number of ways of a multiplexer. Forms maths Geometry Physics 1.
The number of the entries of order is a function of the number of ways of the multiplexer. The combinative network id figure 26 can provide the signal S.
Quad 2-line to 1-line data selectors / multiplexers 74157
The stitching and the logic diagram of this circuit are given on figure A binary comparator is 7157 logical circuit which carries out the comparison between 2 generally noted binary numbers A and B. That is to say to compare the two binary digits A and B. These circuits have several inputs and only one exit. The stitching of this circuit is given on figure 21, while figure 22 represents its logic diagram. We deduce the equation from it from S following: In general, the selected entry carries in index the state corresponding to the combination of the entries of order.
This table, one can extract the equation from the exit S following: The first circuit compares the weak weights of A with the weak weight of B.
Let us examine simplest of the multiplexers, that with 2 ways.
Quad 2-line to 1-line data selectors / multiplexers – Robotech Shop
Electronic forum and Poem. All these considerations are translated in the truth table of figure The integrated circuit is a quadruple multiplexer with 2 ways at entry of common selection.
According to the state of the entry of selection Athe exit S recopy either the D0 entry, or the D1 entry. Click here for the following lesson or ix the synopsis envisaged to this end. Return to the synopsis.
71457 That is translated in the table of figure By putting in series two comparatorsone can compare two numbers 7415 8 bits. If a multiplexer has n input, it is said that it is about a multiplexer with n ways. Dynamic page of welcome. Figure 25 gives the diagram symbolic system and the mechanical equivalent of a multiplexer to 2 ways.
A multiplexer can thus switch data made up of several bits.